Test circuit arrangement for a communication network and test method using same
US4881229A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1987 |
| Grant date | Nov 14, 1989 |
| Priority date | — |
| Expiry date | Oct 21, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/0478
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A built-in test-signal generator (TG) and a built-in error-detection circuit (PE) independent of the test-signal generator are provided in a novel circuit arrangement. In response to an external stimulus, a signal path can be opened at a given point, and the signal from the test-signal generator (TG) can be injected. The signal taken from another, likewise externally selectable point of the signal path is checked in the error-detection circuit (PE); the result is fed out. Such a circuit arrangement is used to advantage where many like circuit arrangements are united in a broadband switching network consisting of a plurality of broadband switching modules. Since the test-signal generators and the error-detection circuits are independent of each other, systems tests can be performed without having to form any additional testing paths. Such a circuit arrangement also facilitates the testing of large-scale-integrated circuits already on the wafer, because no high-frequency test signals have to be applied and taken off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.