Patent · US Expired

Method and circuit configuration of the parallel input of data into a semiconductor memory

US4885748A · kind A · utility

13Cited by
2References
13Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 16, 1988
Grant dateDec 5, 1989
Priority date
Expiry dateMar 16, 2008

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C29/34
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A method and circuit configuration for the parallel input of data items in the form of a test pattern into a block of a semiconductor memory having a plurality of storage cells. For test purposes, data items are simultaneously input in parallel into the storage cells.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.