Dynamic random access memory having open bit line architecture
US4888732A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1988 |
| Grant date | Dec 19, 1989 |
| Priority date | — |
| Expiry date | Feb 18, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory which includes a sense amplifier, first pair of bit lines extending in the opposite directions from the sense amplifier, second pair of bit lines extending in the opposite directions from the sense amplifier and disposed in parallel with the first pair of bit lines, a plurality of word lines disposed in a manner that the word lines perpendicularly intersect with the first and second pairs of bit lines, and a plurality of memory cells disposed at all intersecting points of the word lines and the first and second pairs of bit lines. Two bit lines selected from the first and second pairs of bit lines are coupled to the sense amplifier. Since two bit lines or two groups of memory cells can be disposed at one side of the sense amplifier, space efficiency can be highly improved without damaging the operating characteristics of a dynamic random access memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.