Method of manufacture semiconductor device of the hetero-junction bipolar transistor type
US4889824A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1988 |
| Grant date | Dec 26, 1989 |
| Priority date | — |
| Expiry date | Dec 28, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/944
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a hetero-junction bipolar transistor, especially of gallium arsenide, comprising the step of forming superimposed epitaxial layers for forming a collector layer (1) of the n.sup.+ type, an emitter layer (3) of the n-type, the formation of localized implantations of the p.sup.+ type to obtain the base regions (31,30) or of the n.sup.+ type to obtain collector contact islands (20). This method also includes the formation by a controlled etching into a germanium layer (50) formed at the surface of these layers, of pads having a profile such that their tips define with a very high precision openings (E.sub.1), of which the distance (E.sub.0) between the edges defines the emitter contact region, while their edges have a concavity turned towards the exterior of the device. PA0 Application integrated circuits on gallium arsenide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.