Method for the manufacture of a MESFET comprising self aligned gate
US4889827A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 22, 1988 |
| Grant date | Dec 26, 1989 |
| Priority date | — |
| Expiry date | Sep 22, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/168
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for the manufacture of a MESFET comprising a gate that is self-aligned both with respect to the source and drain regions as well as with respect to the appertaining metallizations, whereby a first metal layer (21), a first dielectric layer (31), and a first lacquer mask layer are applied following doping of the carrier substrate. A trench producing an outer recess in the doping layer (11) is formed by anisotropic etching. A second dielectric layer is isotropically deposited and is anisotropically re-etched except for spacers (51/52) whereby an inner recess (double recess) is produced in the doping layer and, finally, the gate metal (22) is applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.