CMOS device with both p+ and n+ gates
US4890141A · kind A · utility
42Cited by
7References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1988 |
| Grant date | Dec 26, 1989 |
| Priority date | — |
| Expiry date | Jun 29, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/915
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.