Integrated circuit trench cell
US4890144A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1987 |
| Grant date | Dec 26, 1989 |
| Priority date | — |
| Expiry date | Sep 14, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
A multiple element integrated circuit trench cell having at least one vertical field effect transistor (FET) in a wall of a trench in a semiconductor substrate. The cell further comprises a central load device within the trench which is electrically connected to the vertical FET. The central load device may be an active load device, such as another field effect transistor, or a passive load device, such as a resistor. Additionally, a further FET may be present in another wall of the trench or in a lateral orientation adjacent the trench in the semiconductor surface. Two of these multiple element trench cells may be interconnected in various configurations to form conventional static random access memory (SRAM) cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.