Bich-Yen Nguyen
135Patents
32h-index
154Co-inventors
93Inventor score
Filing activity: May 20, 1986 → Jun 14, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7575968B2 | Inverse slope isolation and dual surface orientation integration | Electricity | 516 | Active |
| US4987102A | Process for forming high purity thin films | Electricity | 409 | Expired |
| US6838322B2 | Method for forming a double-gated semiconductor device | Electricity | 176 | Expired |
| US6297095A | Memory device that includes passivated nanoclusters and method for manufacture | Electricity | 142 | Expired |
| US5219793A | Method for forming pitch independent contacts and a semiconductor device having the same | Emerging Cross-Sectional Technologies | 137 | Expired |
| US6541280B2 | High K dielectric film | Electricity | 124 | Expired |
| US7226833B2 | Semiconductor device structure and method therefor | Electricity | 122 | Expired |
| US6184072A | Process for forming a high-K gate dielectric | Electricity | 121 | Expired |
| US6362071B1 | Method for forming a semiconductor device with an opening in a dielectric layer | Electricity | 104 | Expired |
| US4890144A | Integrated circuit trench cell | Emerging Cross-Sectional Technologies | 93 | Expired |
| US5897343A | Method of making a power switching trench MOSFET having aligned source regions | Electricity | 84 | Expired |
| US6770923B2 | High K dielectric film | Electricity | 82 | Expired |
| US6831350B1 | Semiconductor structure with different lattice constant materials and method for forming the same | Electricity | 78 | Expired |
| US6344403B1 | Memory device and method for manufacture | Electricity | 68 | Expired |
| US5408130A | Interconnection structure for conductive layers | Electricity | 67 | Expired |
| US5262352A | Method for forming an interconnection structure for conductive layers | Electricity | 67 | Expired |
| US7018901B1 | Method for forming a semiconductor device having a strained channel and a heterojunction source/drain | Electricity | 65 | Expired |
| US5538922A | Method for forming contact to a semiconductor device | Emerging Cross-Sectional Technologies | 63 | Expired |
| US5639687A | Method for forming an integrated circuit pattern on a semiconductor substrate using silicon-rich silicon nitride | Emerging Cross-Sectional Technologies | 61 | Expired |
| US6413819B1 | Memory device and method for using prefabricated isolated storage elements | Electricity | 61 | Expired |
| US6444512B1 | Dual metal gate transistors for CMOS process | Emerging Cross-Sectional Technologies | 57 | Expired |
| US5300187A | Method of removing contaminants | Emerging Cross-Sectional Technologies | 52 | Expired |
| US4897364A | Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer | Electricity | 52 | Expired |
| US5510278A | Method for forming a thin film transistor | Emerging Cross-Sectional Technologies | 51 | Expired |
| US6518106B2 | Semiconductor device and a method therefor | Electricity | 49 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.