Patent · US Expired

Adder cell for carry-save arithmetic

US4893269A · kind A · utility

1Cited by
5References
3Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 17, 1989
Grant dateJan 9, 1990
Priority date
Expiry dateMar 17, 2009

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F7/501
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

An adder cell in which the sum signal and the carry signal are formed with equal speed is provided for employment in "carry-save" adders, wherein the sum signal and the carry signal are separately forwarded to separate inputs of following adder cells. The circuit of the adder cell is designed such that the sum signal as well as the carry signal each have to traverse only two gates, so that the running times of sum signal and carry signal are approximately identical and shorter than the maximum running time of conventional adder cells.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.