Three-dimensional packaging of semiconductor device chips
US4894706A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1986 |
| Grant date | Jan 16, 1990 |
| Priority date | — |
| Expiry date | Oct 9, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49133
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip carrying member (1) such as a film carrier carrying a chip (10) and elastic spacers (2, 3) are stacked to form an elementary unit with adjusting its thickness. By using an aligning aperture (12) of a thin sheet (1), a plurality of the elementary units are stacked to form a laminated structure. From a side surface of the laminated structure, leads (13) are extended to be connected to a wiring board (241), or after the leads (13) are buried in an insulator (8), the leads (13) and insulator (8) are abraded to form a coplanar surface and then a wiring layer (82) for interconnecting is formed on the abraded surface. A usual chip can be mounted on the chip carrying member (1) without any work with a high accuracy in alignment of the lamination and furthermore with a high accuracy in a lamination pitch of the chip carrying member (1), so that the leads (13) of the chip (10) can be wired precisely and finely. A low cost and high density three-dimensional packaging structure can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.