Stacked MOS transistor flip-flop memory cell

US4894801A · kind A · utility

Assignee

• HITACHI, LTD. · JP

Inventors

• Ryuichi Saito · Maebashi, JP
• Naohiro Momma · Hitachi, JP

Key dates

• Filing date: Jul 24, 1987
• Grant date: Jan 16, 1990
• Expiry date: Jul 24, 2007

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/00

Abstract

A semiconductor memory including two cross-coupled driver MOS transistors respectively having source and drain regions within a semiconductor substrate and each of the drain regions being in ohmic contact with the gate electrode of the other driver MOS transistor. The gate electrodes of the driver MOS transistors are formed in a first-level polycrystalline silicon (polysilicon) layer and the two transfer MOS transistors respectively have their source and drain regions formed in portions of a second-level polysilicon layer. The driver regions are formed so as to be independently brought into ohmic contact with the respective drain regions of the driver MOS transistors, and each of the transfer MOS transistors have a gate electrode effected in a third-level polysilicon layer which also defines a word line. Two load resistors are respectively formed in those regions of the second-level polysilicon layer which extend from the drain regions of the transfer MOS transistors to a power supply potential line, and wherein the corresponding regions of the load resistors are connected to the power supply potential line in the second-level polysilicon layer. Two metallic data lines are respecti…