Method of fabricating a submicron silicon gate MOSFETg21 which has a self-aligned threshold implant
US4895520A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 2, 1989 |
| Grant date | Jan 23, 1990 |
| Priority date | — |
| Expiry date | Feb 2, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/141
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for fabricating submicron silicon gate metal-oxide-semiconductor field effect transistors (MOSFETs) which have threshold and punchthrough implants that are self-aligned to the gate electrode and source and drain regions. A layer of dielectric material (12) is either deposited or grown on the surface of a substrate, and a trench (15), which defines the region of the MOSFET gate electrode, is formed in the dielectric layer. A gate oxide (16) is formed at the exposed substrate at the bottom of the trench, and an implant is performed into the silicon substrate wherever there is gate oxide, but not into the portion of the substrate covered by the original dielectric layer. A layer of polysilicon (20), preferably doped, or another metallic film is then deposited onto the surface. The polysilicon is etched back to the top surface of the dielectric layer, thereby leaving polysilicon in the trench to form the gate electrode (24). The dielectric layer (12) is then etched back preferentially to a thickness approximately equal to the thickness of the gate dielectric, and a high-dose implant is performed through the reduced thickness dielectric layer into the silicon subst…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.