Test circuit for measuring specific contact resistivity of self-aligned contacts in integrated circuits

US4896108A · kind A · utility

Assignee

• American Telephone and Telegraph Company, AT&T Bell Laboratories · US

Inventors

• William T. Lynch · Apex, US
• Kwok Ng · Hackettstown, US

Key dates

• Filing date: Jul 25, 1988
• Grant date: Jan 23, 1990
• Expiry date: Jul 25, 2008

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3011
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A test circuit is described for measuring the specific contact resistivity r.sub.c of self-aligned electrodes contacting underlying diffused regions at a major surface of an underlying semiconductor wafer, as well as the sheet (lateral) resistance r.sub.s of the underlying diffused regions in some embodiments. The test circuit illustratively includes a pair of test MOS or other type of transistors advantageously made by a self-aligned metallization process simultaneously with the other MOS or other type of transistors to be tested. The two test transistors share a common diffused region, a self-aligned common controlled electrode contacting a diffused region underneath it, and a common control electrode. During test operation, both est transistors are kept ON by means of an applied above-threshold control voltage, while a current source forces current through one of the transistors. The resulting voltage, developed across the common controlled electrode and the controlled electrode of the other transistor is a measure of the specific contact resistivity thereat.