Vertical DMOS power transistor with an integral operating condition sensor
US4896196A · kind A · utility
33Cited by
11References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 8, 1988 |
| Grant date | Jan 23, 1990 |
| Priority date | — |
| Expiry date | Sep 8, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
A vertical DMOS or IGBT cell structure with an integral operating condition sensor provided by a sensor region forming a PN junction 65 with an adjacent region of the cell and having a sensor region contact 75 for conducting a test current without interfering with normal operation of the cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.