Semiconductor memory device having trench and stacked polysilicon storage capacitors
US4896197A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 8, 1987 |
| Grant date | Jan 23, 1990 |
| Priority date | — |
| Expiry date | Dec 8, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/377
Abstract
A first impurity region is formed on the inner surface of a trench formed on the major surface of a semiconductor substrate. The trench is filled with a vertical portion of a first electric conductor having a reversed L-shaped cross section through an insulating film. A first transistor having a first impurity region serving as a source/drain region is formed on the semiconductor substrate. A second impurity region serving as a source/drain region of a second transistor is formed on the major surface of the semiconductor substrate and spaced from the trench. A second electric conductor having a reversed L-shaped cross section for connecting the vertical portion to the second impurity region is formed, and a horizontal portion of the second electric conductor is formed to be stacked on a horizontal portion of the first electric conductor with an insulating film formed therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.