Efficient ESD input protection scheme

US4896243A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Amitava Chatterjee · Plano, US
• Charvaka Duvvury · Plano, US

Key dates

• Filing date: Dec 20, 1988
• Grant date: Jan 23, 1990
• Expiry date: Dec 20, 2008

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/601

Abstract

An efficient ESD protection circuit is provided having a resistor (18) disposed between an input pin (12) and the functioning circuitry (22) of an integrated circuit package. A primary switching device (28) is electrically connected between the input pin (12) and a reference voltage pin (14). The resistor (18) comprises an N- well (48) formed within the P- substrate (44) and an N+ diffused reion (50) formed within the N- well (48). A silicided layer (52) is formed over the N+ region (50). The primary switching device (28) is constructed to share the same PN junction (54) utilized by the resistor (18). In constructing the primary switching device (28), a P+ region (70) is formed within the N- well (48). Further, an N+ region (68) is formed within the P- substrate (44). Thus, the primary switching device (40) includes three PN junctions (72, 54, 74) which will conduct at a time prior to, or contemporaneous with, the breakdown of resistor (18).