Recessed contact bipolar transistor and method
US4897703A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1988 |
| Grant date | Jan 30, 1990 |
| Priority date | — |
| Expiry date | Jan 29, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/01
Abstract
Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions. The collector contact region is self aligned to the second sidewall oxide spacer which prevents the contact of base and heavily doped collector. Finally, the oxide cap covering the upper emitter surfaces is removed and emitter, base and collector contact regions are silicided to reduce contact resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.