Floating point circuit with configurable number of multiplier cycles and variable divide cycle ratio
US4901267A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1988 |
| Grant date | Feb 13, 1990 |
| Priority date | — |
| Expiry date | Mar 14, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention optimizes the number and ratio of cycles required among the divide/square root unit, multiplier unit and ALU. An intermediate latch with its own clock is provided at the output of the multiplier half-array in the intermediate stage to feed back data for a second pass for double-precision numbers. The multiplier can then be adjusted for either two-cycle latency mode (for optimizing double-precision multiplies) or three-cycle latency mode (for optimizing single-precision multiplies). A separate divide clock is used for the divide/square root unit, and is synchronized with the multiplier cycle clock on input and output. This allows the divide time to be optimized so that it requires fewer clock cycles when a longer multiplier clock cycle time is used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.