High speed double polycide bipolar/CMOS integrated circuit process
US4902640A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1987 |
| Grant date | Feb 20, 1990 |
| Priority date | — |
| Expiry date | Aug 19, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/124
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mixed bipolar-CMOS self-aligned process and integrated circuit provide a high performance NPN bipolar transistor in parallel to fabrication of a PMOSFET and an NMOSFET. Gate and base contacts are formed in a first polysilicon layer. The base contacts are implanted with P+ ion concentrations for diffusing base contact regions of the substrate in a later drive-in step. Source and drain contacts and emitter contacts are formed in a second polysilicon layer. The source and drain contacts are formed as a unit and then separated into discrete contacts by a spin-on polymer planarization and etch-back procedure. Lightly-doped lateral margins of the source, drain and base regions are ion-implanted in an initial low concentration (e.g. about 10.sup.13 atoms/cm.sup.2). The gate and base contact structures serve as a mask to self-align the implants. Then, the gate and base structures are enclosed in an oxide box having sidewalls. The second polysilicon layer, next deposited, is laterally spaced by the sidewalls from the first layer. The second layer is selectively implanted with dopant ions of appropriate type for each device: N-type for the NMOSFET and P-type for the PMOSFET and the base of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.