Apparatus for self checking of functional redundancy check (FRC) logic
US4903270A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1988 |
| Grant date | Feb 20, 1990 |
| Priority date | — |
| Expiry date | Jun 14, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/267
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit module (200) in which an error detection circuit (234, 263) compares data (204) generated internally on module (200) with data (108) generated externally from another substantially identical module (100). An error detect output (238) is asserted upon the condition that data (204) generated internally on module (200) and data (108) generated externally from module (100) do not match. A circuit (222, 224) alters the internally generated data (204) by injecting erroneous data into the internally generated data (204) to thereby generate altered data (230). Error anticipation control logic (210) generates a test condition (214, 216), which corresponds to the expected error condition caused by altered data. Comparison circuit (242) compares the actual error detect output (238, 240) with expected error detect output (214, 215). An error output (244) is asserted if the actual error detect output (238, 240) and the expected error detect output (214, 216) do not match.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.