MOS adder with minimum pass gates in carry line
US4905180A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 1988 |
| Grant date | Feb 27, 1990 |
| Priority date | — |
| Expiry date | Dec 16, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A metal-oxide-semiconductor (MOS) partitioned carry lookahead adder fabricated from a plurality of four bit slice blocks. Each block provides four sum signals and provides a block carry signal. The blocks are organized into groups of optimum size with logic in each group to generate a group propagate signals. Each block has a block carry line with a single transistor connected between the input and output terminals of the block. The blocks employ an intermediate carry circuit for computing sums in place of full adders. In addition, there is a main carry line with transistors controlled by the group propagate signals for a 32 bit adder, the maximum pass gate delay in the carry chain is three pass gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.