Sudarshan Kumar
32Patents
8h-index
27Co-inventors
75Inventor score
Filing activity: Dec 16, 1988 → Sep 15, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5661675A | Positive feedback circuit for fast domino logic | Physics | 37 | Expired |
| US4905180A | MOS adder with minimum pass gates in carry line | Physics | 14 | Expired |
| US5581497A | Carry skip adder with enhanced grouping scheme | Physics | 13 | Expired |
| US5136539A | Adder with intermediate carry circuit | Physics | 12 | Expired |
| US6707318B2 | Low power entry latch to interface static logic with dynamic logic | Electricity | 11 | Expired |
| US5471414A | Fast static CMOS adder | Physics | 10 | Expired |
| US6952118B2 | Gate-clocked domino circuits with reduced leakage current | Electricity | 9 | Expired |
| US6631093B2 | Low power precharge scheme for memory bit lines | Physics | 8 | Expired |
| US6124737A | Low power clock buffer having a reduced, clocked, pull-down transistor | Electricity | 8 | Expired |
| US6351151B2 | Method and apparatus for reducing soft errors in dynamic circuits | Electricity | 8 | Expired |
| US5579254A | Fast static CMOS adder | Physics | 8 | Expired |
| US6820106B1 | Method and apparatus for improving the performance of a floating point multiplier accumulator | Physics | 8 | Expired |
| US5900744A | Method and apparatus for providing a high speed tristate buffer | Electricity | 7 | Expired |
| US6292029A | Method and apparatus for reducing soft errors in dynamic circuits | Electricity | 7 | Expired |
| US6629194B2 | Method and apparatus for low power memory bit line precharge | Physics | 5 | Expired |
| US6833735B2 | Single stage pulsed domino circuit for driving cascaded skewed static logic circuits | Electricity | 5 | Expired |
| US6058403A | Broken stack priority encoder | Physics | 5 | Expired |
| US6023767A | Method for verifying hold time in integrated circuit design | Physics | 4 | Expired |
| US6127850A | Low power clock buffer with shared, clocked transistor | Electricity | 4 | Expired |
| US6205463A | Fast 2-input 32-bit domino adder | Physics | 4 | Expired |
| US5944777A | Method and apparatus for generating carries in an adder circuit | Physics | 3 | Expired |
| US5889693A | CMOS sum select incrementor | Physics | 3 | Expired |
| US5608741A | Fast parity generator using complement pass-transistor logic | Physics | 2 | Expired |
| US6111435A | Low power multiplexer with shared, clocked transistor | Electricity | 2 | Expired |
| US6266757A | High speed four-to-two carry save adder | Physics | 2 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.