Enclosed buried channel transistor
US4906588A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 23, 1988 |
| Grant date | Mar 6, 1990 |
| Priority date | — |
| Expiry date | Jun 23, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
Abstract
An enclosed buried channel device includes a buried channel region (26) disposed under a gate electrode (24). Source and drain regions (54) and (56) are formed on either side of gate electrode (26). The source/drain regions (54) and (56) are separated from the various channel region (26) by isolating regions of N-type material (58) and (60), respectively. The isolating regions (58) and (60) are operable to be inverted during normal operation of the transistor when the transistor is conducting, but are operable to isolate fields on the drain side of the transistor from the buried channel region (26) to lower the leakage current of the device in the off state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.