Semiconductor integrated circuit device having power down mode
US4906862A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 7, 1988 |
| Grant date | Mar 6, 1990 |
| Priority date | — |
| Expiry date | Oct 7, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17708
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device has a plurality of terminals, an internal circuit for receiving input signals from the terminals and for outputting output signals to the terminals, where the internal circuit is enabled by a chip enable signal and disabled by a chip disable signal, a non-volatile memory for storing a pin select signal which designates at least a selected one of the terminals as a chip enable control terminal for receiving a control signal which has a first logic level when instructing a power down mode of the semiconductor integrated circuit device, and a buffer part coupled to the terminals and the non-volatile memory for generating the chip enable signal and the chip disable signal responsive to the pin select signal and the control signal. The buffer part generates the chip enable signal when the control signal received by the selected one terminal has a second logic level and generates the chip disable signal when the control signal received by the selected one terminal has the first logic level to thereby set an operation mode of the semiconductor integrated circuit device to the power down mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.