Cache tag comparator with read mode and compare mode
US4907189A · kind A · utility
15Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 1988 |
| Grant date | Mar 6, 1990 |
| Priority date | — |
| Expiry date | Aug 8, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache TAG, which has a compare mode, an and/or/invert mode, and a read mode, has a programmable comparator which receives an external data signal and an output from an array of memory cells and provides an output to a secondary amplifier. The secondary amplifier provides an output to a match comparator in the compare mode and the and/or/invert mode and to an output buffer in the read mode. The programmable comparator is programmable according to the mode of the cache TAG. The compartor uses selectively enabled transmission gates which provide minimal delay in providing the appropriate data to the secondary sense amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.