Dual-rail processor with error checking at single rail interfaces
US4907228A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1987 |
| Grant date | Mar 6, 1990 |
| Priority date | — |
| Expiry date | Sep 4, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual processor computer system with error checking includes a first processing system for executing a series of instructions including output instructions. A second processing system executes the series of instructions independently of and in synchronism with the first processing system. Shared resource devices are coupled to the first and second processing systems for receiving data from output instructions from the first and second processing systems substantially simultaneously. Error checking devices are located downstream of the shared resource means for checking the data received from the first and second processing systems only following a write operation into the shared resource means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.