Split array binary multiplication
US4910701A · kind A · utility
15Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1987 |
| Grant date | Mar 20, 1990 |
| Priority date | — |
| Expiry date | Sep 24, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49994
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for binary multiplication based upon the modified Booth algorithm incorporating a Booth multiplex decoder, partial modified Booth arrays and partial product reduction adders. The system is comprised of Booth multiplexer cells, Booth multiplexer and adder cells, sign extension cells, and full adder cells interconnected such that the total adder delay through the system is n/4+1 adder delays where n is the number of bits in the multiplier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.