Programmable logic device with array blocks with programmable clocking
US4912342A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1989 |
| Grant date | Mar 27, 1990 |
| Priority date | — |
| Expiry date | Sep 14, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/49113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array is provided to allow certain inputs to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.