Bonding of aligned conductive bumps on adjacent surfaces
US4912545A · kind A · utility
44Cited by
5References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 16, 1987 |
| Grant date | Mar 27, 1990 |
| Priority date | — |
| Expiry date | Sep 16, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bump bonding process and product are disclosed in which both pressure and heating are used in situations where the temperature should not exceed a predetermined amount, e.g., bonding of a photoconductor array to a module containing electronic processing devices. The bonding process involves eutectic alloying of indium and bismuth, allowing welding of the bumps at a temperature substantially below the two metals' melting points. In one version of the invention, bumps on adjacent substrates are directly aligned. In another version, each bump on one substrate is wedged between a pair of bumps on the other substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.