Programmable logic device
US4912677A · kind A · utility
15Cited by
4References
6Claims
0Family size
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Key dates
| Filing date | Jun 10, 1988 |
| Grant date | Mar 27, 1990 |
| Priority date | — |
| Expiry date | Jun 10, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17708
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device includes an AND array; an OR array; a buffer circuit connected between the AND array and OR array; and a number of decoder arrangements operatively connected to the AND array and OR array. By constituting the buffer such that the AND array and OR array are electrically associated even in a write operation of data, namely, the buffer is brought to an enable state, a logic verify of the buffer becomes unnecessary and, accordingly, a verify/check of written data can be carried out both easily and efficiently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.