Dynamic random access memory device with staggered refresh
US4912678A · kind A · utility
84Cited by
3References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 22, 1988 |
| Grant date | Mar 27, 1990 |
| Priority date | — |
| Expiry date | Sep 22, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory (DRAM) comprises a divided plurality of memory array blocks. Each memory array block comprises a memory array having memory cells and a sense amplifier. In refresh operation, activating signals for activating each of the sense amplifiers are outputted. The output timings of the activating signals are different from each other, so that each of the sense amplifiers are activated at different timings. Consequently, a peak value of the current consumed by the activation of the sense amplifiers can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.