Method of making Bicmos devices

US4914048A · kind A · utility

Assignee

• STC PLC · GB

Inventors

• Peter D. Scovell · Chelmsford, GB
• Peter F. Blomley · Bishop's Stortford, GB
• Roger L. Baker · Chelmsford, GB

Key dates

• Filing date: Dec 16, 1987
• Grant date: Apr 3, 1990
• Expiry date: Dec 16, 2007

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/01

Abstract

A bipolar transistor structure (1) which can be used in an integrated circuit where bipolar (1) and CMOS transistors (2,3) are formed simultaneously on one substrate. In integrated circuit form the material, for example polycrystalline silicon, used for the gates (11,21) of the CMOS transistors is also used for the emitters (29) of the bipolar transistors, the collectors of the bipolar devices are comprised by doped wells (5) in the substrate (4) and the base contacts of the bipolar devices are comprised by regions (27,27a) equivalent to source and drain regions (17,18) of the n-well MOS transistors and bridged by base implants (28). The conventional CMOS processing is modified by the addition of two masking steps and one implant (base implant). One masking step defines the area for the base implant (18) and the other masking step defines an area of the oxide (30) over the base implant which must be removed to allow contact between the polycrystalline silicon (29), which is suitably doped to provide the emitter, and the base ( 27,27a,28). The base contacts are produced in a semi-self-aligned manner.