Method for making a vertical power DMOS transistor with small signal bipolar transistors
US4914051A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1988 |
| Grant date | Apr 3, 1990 |
| Priority date | — |
| Expiry date | Dec 9, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/126
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicon integrated circuit includes a vertical power DMOS transistor and a vertical NPN transistor in separate epitaxial pockets by a method including simultaneously forming a plurality of D-well regions in the DMOS transistor and the base region in the NPN transistor, and including simultaneously forming the elemental source regions and the emitter region. N-type buried layers are provided simultaneously in the DMOS and the NPN transistors, respectively. Also formed simultaneously are two N+ plugs connecting the two buried layers, respectively, to the epitaxial surface of the integrated circuit die. None of these economically attractive simultaneous steps requires deviation in either device from optimum geometries. Also disclosed are compatible and integrated steps for forming small signal CMOS transistors. This method also includes a full self-alignment of gate, source and channel regions in the DMOS transistor as well as in the CMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.