Grooved DMOS process with varying gate dielectric thickness
US4914058A · kind A · utility
207Cited by
6References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 29, 1987 |
| Grant date | Apr 3, 1990 |
| Priority date | — |
| Expiry date | Dec 29, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/168
Abstract
Disclosed is a process for making a DMOS, including lining a groove with a dielectric material to form an inner groove having sidewalls extending through the bottom of the first groove, and lining the inner groove with a dielectric material to obtain increased thickness of the gate dielectric on the sidewalls of the inner groove.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.