Pull up circuit for sense lines in a semiconductor memory
US4914631A · kind A · utility
35Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1988 |
| Grant date | Apr 3, 1990 |
| Priority date | — |
| Expiry date | Sep 30, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array (e.g., DRAM) is provided with a potential maintenance circuit which provides sufficient current to maintain a high potential node of the memory array at a predetermined potential. The potential maintenance circuit is gated ON after receipt of a clock signal and gated OFF at the predetermined potential. This permits the high voltage node to be maintained, while reducing current requirements. The invention is particularly useful when used in conjunction with a circuit which rapidly pulls up the high node to a value of V.sub.CC -V.sub.T (where VT is a threshold voltage of a transistor).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.