Semiconductor devices
US4916517A · kind A · utility
2Cited by
5References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1988 |
| Grant date | Apr 10, 1990 |
| Priority date | — |
| Expiry date | Dec 5, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/124
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidised sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidised sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.