Process for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chip

US4918026A · kind A · utility

Assignee

• DELCO ELECTRONICS CORPORATION · US

Inventors

• Walter K. Kosiak · Kokomo, US
• Douglas R. Schnabel · Kokomo, US
• Jonathan Mann · Quakertown, US
• Jack D. Parrish · Kokomo, US
• Paul R. Rowlands, III · Kokomo, US

Key dates

• Filing date: Mar 17, 1989
• Grant date: Apr 17, 1990
• Expiry date: Mar 17, 2009

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516

Abstract

A process is used to form in a common substrate a PMOS transistor of the lightly doped drain (LDD) type, an NMOS transistor of the LDD type and a vertical n-p-n bipolar transistor. In particular: the steps used to form an n-type well for the PMOS transistor, and an n-type drain extension well for the NMOS transistor, are also used to form the n-type collector of the bipolar transistor; the steps used to form the p-type extension well for the PMOS transistor are also used to form the p-type base of the bipolar transistor, the source/drain implantation step for the NMOS transistor is also used to form the emitter and a contact region for the collector of the bipolar transistor; and the source/drain implantation step for the PMOS transistor is used to form a contact region for the base of the bipolar transistor.