Jack D. Parrish
6Patents
4h-index
8Co-inventors
50Inventor score
Filing activity: Mar 17, 1989 → Mar 29, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5047358A | Process for forming high and low voltage CMOS transistors on a single integrated circuit chip | Electricity | 94 | Expired |
| US4918026A | Process for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chip | Electricity | 80 | Expired |
| US5366916A | Method of making a high voltage implanted channel device for VLSI and ULSI processes | Electricity | 42 | Expired |
| US5734186A | CMOS voltage clamp | Emerging Cross-Sectional Technologies | 4 | Expired |
| US5869366A | Method for forming voltage clamp having a breakdown voltage of 40 Vdc | Emerging Cross-Sectional Technologies | 4 | Expired |
| US8631905B2 | Ladder apparatus | Fixed Constructions | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.