Failure detection for partial write operations for memories
US4918695A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1988 |
| Grant date | Apr 17, 1990 |
| Priority date | — |
| Expiry date | Aug 30, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1056
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A failure detection system for variable field partial write system for merging data bits in a memory word upon programmable request is described. The variable bit field can be selected for any number of bit positions from a single bit up to and including a full data word, where data words are comprised of a predetermined number of bytes each containing a predetermined number of bits. A Start Bit Code defines the location of the start of the bit field to be written and an End Bit Code defines the bit after the last bit that is to be merged and written. Write and Read Data to be used in the partial merge operation are stored in a Merge Register along with a code derived from the Start and End Code bits. The bits not used are stored in a Non-Merge Register. Parities are compared to verify that a parity error did not occur when the Merge Register was loaded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.