Virtual address table look aside buffer miss recovery method and apparatus
US4920477A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1987 |
| Grant date | Apr 24, 1990 |
| Priority date | — |
| Expiry date | Apr 20, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor has a central processing unit and at least one pipelined memory controller circuitry. The central processing unit addresses data in the memory using a virtual address memory table lookaside buffer and features a data miss recovery circuitry wherein, after a memory access error condition has been detected, the instruction causing the error condition, and those instructions entering the memory pipeline after the instruction causing the error condition, are replayed. The method and apparatus for replaying the instructions use first in-first out buffers for storing the virtual address data and instruction status data relating to each memory access instruction. That stored data is then retrieved after an error condition is detected so that the instruction sequence, beginning at the data miss, can be replayed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.