Semiconductor memory device having sub bit lines
US4920517A · kind A · utility
24Cited by
1References
7Claims
0Family size
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Key dates
| Filing date | Apr 18, 1988 |
| Grant date | Apr 24, 1990 |
| Priority date | — |
| Expiry date | Apr 18, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory which includes a memory cell array, sense amplifiers disposed at both side of the memory cell array, and sub bit lines coupled to the sense amplifiers. The sub bit lines are coupled to data busses through middle amplifiers. By use of such memory architecture, higher integration of DRAM can be realized. Also, handling of super large bit data more than 1024 bit becomes possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.