Boost clock circuit for driving redundant wordlines and sample wordlines
US4922128A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 1989 |
| Grant date | May 1, 1990 |
| Priority date | — |
| Expiry date | Jan 13, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A boost clock signal generator which provides a boost clock signal from a pair of phase clocks. A pair of differentially-connected FET transistors which generate a boost clock signal. The transistors have drain connections connected to each of two clock signals, and commonly connected sources which form an output terminal for the boost clock signal. A series pass FET transistor is connected with each gate of the differential transistors for maintaining the gate at a floating voltage potential. A pair of capacitive elements couple the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor. A first and second logic circuit are connected to the series pass FET transistors for enabling one or the other of the differnetially-connected FET transistors into conduction. The pair of capacitive coupling elements coupling the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor increase switching speed of the clock signal generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.