Patent · US Expired

Testable redundancy decoder of an integrated semiconductor memory

US4922134A · kind A · utility

15Cited by

18References

8Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Kurt Hoffmann · Taufkirchen, DE
Oskar Kowarik · Grafing, DE
Rainer Kraus · Hersbruck, DE
Bernhard Lustig · Munich, DE
Hans-Dieter Oberle · Puchheim, DE

Key dates

Filing date	Feb 10, 1989
Grant date	May 1, 1990
Priority date	—
Expiry date	Feb 10, 2009

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/785
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A redundancy decoder of an integrated semiconductor memory having a plurality of decoder stages containing a switching transistor and a separable connection having respective conditions in which the separable connection is severed and intact, as well as at least one charging transistor, comprising, in each of the decoder stages, an addressing circuit connected to and between the switching transistor and the separable connection of the respective decoder stages, the addressing circuit being electrically simulatable when the respective separable connection is in the intact condition thereof.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.