High speed digital counter
US4924484A · kind A · utility
5Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1988 |
| Grant date | May 8, 1990 |
| Priority date | — |
| Expiry date | Oct 27, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed counter circuit for counting electrical pulses includes a master/slave flip-flop at the input stage of the counter. An AND gate logically ANDs the pulses being counted with the master output to produce a first gating signal. A plurality of cascade coupled flip-flops each having a slave and an inverse slave output are provided. The clock input to each cascade coupled flip-flop is produced by the logical OR of the electrical pulses being counted, the first gating signal and the slave output of all preceding flip-flops of the counter. The counter output is provided by the inverse slave output of each flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.