Method and apparatus for processing postnormalization and rounding in parallel
US4926370A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1989 |
| Grant date | May 15, 1990 |
| Priority date | — |
| Expiry date | Apr 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49957
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for processing postnormalization and rounding in parallel in floating point arithmetic circuits. The fractional result of a floating point arithmetic operation is simultaneously passed to a normalized circuit and a round circuit, and the first two bit positions of the fractional result are examined. If the 2-bit format is 1.X the round circuit is activated; if the 2-bit format is 0.1X the fractional result is shifted left one position and the round circuit is activated; if the 2-bit format is in neither of the above formats the normalize circuit is activated. In no event is it necessary to activate sequentially the normalize circuit and the round circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.