Daniel Stasiak
43Patents
10h-index
64Co-inventors
78Inventor score
Filing activity: Apr 17, 1989 → Dec 20, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6504212B1 | Method and apparatus for enhanced SOI passgate operations | Physics | 70 | Expired |
| US6002292A | Method and apparatus to control noise in a dynamic circuit | Electricity | 51 | Expired |
| US4941120A | Floating point normalization and rounding prediction circuit | Physics | 48 | Expired |
| US6668358B2 | Dual threshold gate array or standard cell power saving library circuits | Physics | 34 | Expired |
| US4926370A | Method and apparatus for processing postnormalization and rounding in parallel | Physics | 29 | Expired |
| US6429689B1 | Method and apparatus for controlling both active and standby power in domino circuits | Electricity | 22 | Expired |
| US6201431A | Method and apparatus for automatically adjusting noise immunity of an integrated circuit | Electricity | 17 | Expired |
| US6934658B2 | Computer chip heat responsive method and apparatus | Emerging Cross-Sectional Technologies | 16 | Expired |
| US6925549B2 | Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages | Physics | 16 | Expired |
| US6635518B2 | SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies | Electricity | 10 | Expired |
| US6232799A | Method and apparatus for selectively controlling weak feedback in regenerative pass gate logic circuits | Electricity | 10 | Expired |
| US7233188B1 | Methods and apparatus for reducing power consumption in a processor using clock signal control | Emerging Cross-Sectional Technologies | 9 | Expired |
| US6326814A | Method and apparatus for enhancing noise tolerance in dynamic silicon-on-insulator logic gates | Physics | 8 | Expired |
| US7535020B2 | Systems and methods for thermal sensing | Electricity | 8 | Active |
| US7484187B2 | Clock-gating through data independent logic | Physics | 7 | Active |
| US6329846A | Cross-coupled dual rail dynamic logic circuit | Electricity | 7 | Expired |
| US7044633B2 | Method to calibrate a chip with multiple temperature sensitive ring oscillators by calibrating only TSRO | Electricity | 6 | Expired |
| US7605612B1 | Techniques for reducing power requirements of an integrated circuit | Emerging Cross-Sectional Technologies | 6 | Active |
| US7058131B2 | Signal transmission system with programmable voltage reference | Electricity | 6 | Expired |
| US8020138B2 | Voltage island performance/leakage screen monitor for IP characterization | Physics | 5 | Active |
| US6879928B2 | Method and apparatus to dynamically recalibrate VLSI chip thermal sensors through software control | Physics | 4 | Expired |
| US7656237B2 | Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic | Emerging Cross-Sectional Technologies | 3 | Active |
| US7720667B2 | Method and system for estimating power consumption of integrated circuitry | Physics | 3 | Active |
| US7343499B2 | Method and apparatus to generate circuit energy models with multiple clock gating inputs | Emerging Cross-Sectional Technologies | 3 | Expired |
| US7346866B2 | Method and apparatus to generate circuit energy models with clock gating | Physics | 3 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.