Residue checking apparatus for detecting errors in add, subtract, multiply, divide and square root operations
US4926374A · kind A · utility
12Cited by
6References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 23, 1988 |
| Grant date | May 15, 1990 |
| Priority date | — |
| Expiry date | Nov 23, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention concerns a residue checking apparatus which uses common circuitry to conduct residue checking of the outcome of an arithmetic operation which may be an add, a subtract, a multiply, a divide, or a square root operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.