Mark Michael Schaffer
24Patents
9h-index
28Co-inventors
75Inventor score
Filing activity: Nov 23, 1988 → Oct 18, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6055584A | Processor local bus posted DMA FlyBy burst transfers | Physics | 70 | Expired |
| US6081860A | Address pipelining for data transfers | Physics | 50 | Expired |
| US5884051A | System, methods and computer program products for flexibly controlling bus access based on fixed and dynamic priorities | Physics | 34 | Expired |
| US5925118A | Methods and architectures for overlapped read and write operations | Physics | 32 | Expired |
| US5862353A | Systems and methods for dynamically controlling a bus | Physics | 32 | Expired |
| US4926374A | Residue checking apparatus for detecting errors in add, subtract, multiply, divide and square root operations | Physics | 12 | Expired |
| US5848436A | Method and apparatus for efficiently providing data from a data storage medium to a processing entity | Physics | 12 | Expired |
| US5926831A | Methods and apparatus for control of speculative memory accesses | Physics | 12 | Expired |
| US6504854B1 | Multiple frequency communications | Physics | 9 | Expired |
| US6047336A | Speculative direct memory access transfer between slave devices and memory | Physics | 8 | Expired |
| US7395361B2 | Apparatus and methods for weighted bus arbitration among a plurality of master devices based on transfer direction and/or consumed bandwidth | Physics | 7 | Expired |
| US6032238A | Overlapped DMA line transfers | Physics | 5 | Expired |
| US7209998B2 | Scalable bus structure | Physics | 3 | Expired |
| US8615638B2 | Memory controllers, systems and methods for applying page management policies based on stream transaction information | Physics | 3 | Active |
| US9064050B2 | Arbitrating bus transactions on a communications bus based on bus device health information and related power management | Emerging Cross-Sectional Technologies | 3 | Active |
| US9152595B2 | Processor-based system hybrid ring bus interconnects, and related devices, processor-based systems, and methods | Emerging Cross-Sectional Technologies | 3 | Active |
| US6052745A | System for asserting burst termination signal and burst complete signal one cycle prior to and during last cycle in fixed length burst transfers | Physics | 2 | Expired |
| US8838861B2 | Methods and apparatuses for trace multicast across a bus structure, and related systems | Physics | 1 | Active |
| US7185123B2 | Method and apparatus for allocating bandwidth on a transmit channel of a bus | Physics | 1 | Expired |
| US8861410B2 | Method and apparatus for scalable network transaction identifier for interconnects | Electricity | 0 | Active |
| US8028143B2 | Method and apparatus for transmitting memory pre-fetch commands on a bus | Physics | 0 | Expired |
| US8599886B2 | Methods and apparatus for reducing transfer qualifier signaling on a two-channel bus | Emerging Cross-Sectional Technologies | 0 | Active |
| US7617343B2 | Scalable bus structure | Physics | 0 | Active |
| US7913021B2 | Scalable bus structure | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.