Divided bit line type dynamic random access memory with charging/discharging current suppressor
US4926382A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1988 |
| Grant date | May 15, 1990 |
| Priority date | — |
| Expiry date | Nov 23, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A divided bit line type dynamic semiconductor memory device comprises parallel main bit line pairs, divided bit line pairs provided at each main bit line pair, parallel word lines insulatively crossing the divided bit line pairs, and memory cells provided at the cross points between the divided bit line pairs and the word lines. First sense amplifiers are coupled to the divided bit line pairs. Second sense amplifiers are coupled to the main bit line pairs. First transfer gate sections are coupled between the divided bit line pairs and the main bit line pairs, respectively. Second transfer gate sections are coupled between the main bit line pairs and the second sense amplifier circuits, respectively. A charging/discharging current suppressor is provided which, in both of the read and restoring modes, restricts the amplitude of the potential change, due to charging/discharging, of a specifi main bit line pair associated with a selected divided bit line pair including a selected cell to be smaller than a full potential change defined by the source voltage and ground potential of the device, whereby a charging/discharging cuffent flowing through the specific main bit line pair is reduc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.