Coherent cache structures and methods
US4928225A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1988 |
| Grant date | May 22, 1990 |
| Priority date | — |
| Expiry date | Sep 2, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly, on a one-to-one basis maps a range of physical address bits into a first section of the operand cache storage. An associative directory multiply maps physical addresses outside of the range into a second section of the operand cache storage section. All stack frames of user programs to be executed on the time-shared basis are stored in the first section, so cache misses due to stack operations are avoided. An instruction cache haivng various categories of instructions stores a group of status bits identifying the instruction category with each instruction. When a context switch occures, only instructions of the category least likely to be used in the near future are cleared decreasing delays due to clearing of the instruction cache as a result of context switches. A page-mapped I/O cache structure interfaces by a large number of I/O channels which regard a single I/O cache as an exclus…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.